This invention relates generally to integrated circuit manufacturing methods.
As is known in the art, high speed, digital logic circuits have been designed using gallium-arsenide (GaAs) Schottky-gate MESFET (metal electrode semiconductor field effect transistor) technology by combining the high mobility characteristics of GaAs and the short channel lengths of Schottky-gate depletion mode transistors. However, yields have been relatively low because, in order to achieve channel lengths in the order of a micron, complex photolithographic techniques are at their diffraction imposed limits, and, further, gallium arsenide material is relatively difficult material to prepare and cannot readily be subjected to temperatures required for solid state diffusion.
As is further known in the art, it is frequently desirable to form at the output portion of a logic gate an N channel and P channel field effect transistor in order to form a "complementary" pair of interconnected transistors on a single crystal substrate which provides low static power dissipation and large output capacitance drive capability. Such complementary pair formation is not generally practical with a substrate of GaAs.